1. Field of the Invention
The present invention generally relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a buried impurity layer in a deep position of a semiconductor substrate. The present invention also relates to a resist composition used in this method.
2. Description of the Background Art
FIGS. 8A-8E are partial sectional views of a semiconductor device showing sequential steps of forming an impurity layer near the surface (shallow portion) of a semiconductor substrate.
Referring to FIG. 8A, a resist film 2 of 0.5 .mu.m-2 .mu.m, in most cases 1 .mu.m-1.5 .mu.m in thickness is formed on a semiconductor substrate 1.
The reason why the thickness of the resist film may be so thin is set forth in the following. In order to form impurities near the surface (at most 2 .mu.m in depth) of a semiconductor substrate, the implantation energy is not more than 300 keV in boron implantation and not more than 600 keV in phosphorus implantation. Even a thin resist film of less than 2 .mu.m can sufficiently block impurity ions in such a low level of energy.
Referring to FIGS. 8A and 8B, resist film 2 is patterned to a desired configuration to form a resist pattern 8.
If necessary, resist pattern 8 is subjected to far ultraviolet radiation (commonly called Deep UV cure), post baked process, or the like to prevent sagging of the resist configuration caused by a rise in temperature during a subsequent process of ion implantation, or to reduce the amount of gas generation from the resist film (caused by remaining solvent dissolving the resist, or water introduced during developing and rinsing).
Referring to FIGS. 8C and 8D, impurity ions 9 are introduced to the main surface of a semiconductor substrate 1 with resist pattern 8 as a mask to form an impurity ion implantation layer 9a in the main surface of semiconductor substrate 1.
Referring to FIGS. 8D and 8E, resist pattern 8 is removed by ashing using plasma including oxygen. Ashing removal of resist pattern 8 is carried out in an asher.
According to the above-described conventional art, ions are implanted with low energy, whereby an impurity layer is formed near the surface (shallow portion) of a semiconductor substrate.
Recently, the technique is required to form a buried impurity layer in a semiconductor substrate by implanting impurity ions by high energy into the main surface of a semiconductor substrate, as shown in FIG. 9.
FIG. 10A shows the relationship between ion implantation energy and the required minimum film thickness of a resist as a mask in implanting boron ions to the surface of a semiconductor substrate using a resist mask. FIG. 10B shows the relationship between ion implantation energy and the required minimum film thickness of a resist as a mask in implanting phosphorus ions to the surface of a semiconductor substrate using a resist mask.
Referring to FIGS. 10A and 10B, it is appreciated that a resist of at least 3 .mu.m, approximately 3-6 .mu.m in film thickness is required to efficiently serve as a mask when the ion implantation energy exceeds 1 MeV.
However, a resist that can be formed in a film thickness exceeding 3 .mu.m is not substantially known. In general, the concentration of the resist solid in a resist solution must be increased to increase viscosity of the resist solution in order to increase the film thickness. However, there is limitation in increasing the concentration of the resist solid in the resist solution. If attempt is made to increase the concentration to obtain a film thickness of more than 3 .mu.m, the resist solid cannot be dissolved in the resist solvent. Even if a resist solution of required viscosity is temporarily obtained, it is unstable over time with the problem that photosensitive agent is precipitated during storage.
As a resist that solves the above-described problem and that allow formation of a resist film exceeding the thickness of 3 .mu.m, "AZ4620" (a product of Hoechst Limited) is known. Such a resist has the problems set forth in the following.
FIG. 11 is a diagram showing the steps of forming a buried impurity layer in a semiconductor substrate using AZ4620.
Referring to (a) in FIG. 11, AZ4620 is applied on a semiconductor substrate (silicon substrate) 1 to be prebaked on a hot plate at 90.degree. C. for 150 seconds to result in a resist film 2 having a film thickness of 5.0 .mu.m. At least 120 seconds are required for the prebaking time to obtain a uniform film thickness. A prebaking time period of approximately 60 seconds is sufficient for a resist having the normal standard film thickness (0.5 .mu.m-2 .mu.m).
Referring to (b) in FIG. 11, resist film 2 is selectively exposed with a g-line stepper "NSR1505G6E" (a product of Nikon Corporation) using a desired reticle. Then, paddle developing was carried out for 120 seconds using a developer of Tokyo Ohka Kogyo Co., Ltd. "NMD-3" (2.38 wt %) to obtain a resist pattern 8. The sensitivity required to obtain a desired dimension is 1500 msec. This is considerably low in sensitivity in comparison with a resist of standard thickness (normally 150 msec-500 msec). The resolution was 2 .mu.m in line-and-space.
This resist had a problem set forth in the following during the developing process. A slightly soluble layer 8a formed at the sidewall of resist pattern 8 that is not dissolved in the developer is partially peeled off during the developing step. This leads to a problem that the peeled off portion adheres to an exposed portion, i.e. a portion 1a where resist is dissolved, as a resist residue.
It is assumed that slight soluble layer 8a is an azoxy compound shown in FIG. 13 or an azo compound shown in FIG. 14 which is produced by azo coupling reaction between the photosensitive agent and resin. The reason why such a slightly soluble layer 8a is easily generated is set forth in the following. In a resist such as AZ4620 that is improved to increase the film thickness, the amount of photosensitive agent is reduced in order to increase the transparency of the resist. This will reduce the dissolution suppression effect of the resist with respect to a developer caused by the photosensitive agent in non-exposure portions. To compensate for this reduction of dissolution suppression effect, the composition of the resist material is devised such that azo compound or the like that is not easily dissolved in the developer is generated at the surface of the resist. However, this will generate a slight soluble layer at the sidewall of a resist pattern, which in turn yields the above-described problems. For the sake of simplicity, slight soluble layer 8a is not shown in the following drawings.
Referring to (c) in FIG. 11, a deep UV cure process is carried out to improve heat resistance of resist pattern 8. The reason why a deep UV cure process is carried out will be described in details afterwards. By irradiation of deep UV light, i.e. light of a wavelength not more than 300 nm, curing reaction proceeds from the surface to the interior of the resist, whereby sagging of the resist configuration is prevented by the heating during a subsequent post baking step or ion implantation step. However, during this deep UV cure processing step, the generated amount of N.sub.2 gas is increased caused by increase of the photosensitive agent amount due to the resist film thickness being increased and by increase of the exposure amount due to reduction in sensitivity. (The photosensitive agent is decomposed while discharging N.sub.2 gas as shown in FIG. 12). By generation of this N.sub.2 gas, fine particles of the resist are spattered (called cure foaming) to result in contamination.
Referring to (d) in FIG. 11, a baking process (called post baking) in an oven or the like is carried out to draw out gas from the resist film prior to ion implantation. In order to draw out gas efficiently, post baking is carried out in an oven for 60 minutes at 150.degree. C.
Referring to (e) in FIG. 11, impurity ions 9 are implanted at high energy using a thick resist pattern 8. This results in formation of a buried impurity layer 9a at a deep position in semiconductor substrate 1.
The reason why the deep UV cure process shown in (c) in FIG. 11 is required will be described hereinafter.
FIGS. 16A-16C show the result of heat resistance evaluation of the resist pattern at the state shown of (b) in FIG. 11. FIG. 16A shows a sectional view of a resist right after developing. FIG. 16B shows a sectional view of a resist after the resist pattern is heated on a hot plate for 5 minutes at 120.degree. C. FIG. 16C shows a sectional view of a resist after heating at 150.degree. C. for 5 minutes. Comparing FIGS. 16B and 16C, it is appreciated that the rectangular shape of the sectional configuration of the resist pattern is degraded when heated to a temperature exceeding 120.degree. C. The resist is reduced in film thickness in the proximity of the edge of the resist pattern. If the deep UV cure process of (c) in FIG. 11 is not carried out, i.e. if the steps of (d) and (e) in FIG. 11 are carried out directly after the step of (b), heat sagging will occur at the proximity of the edge of the resist pattern due to heating during a post baking step or during impurity ion implantation. This means that ions will not be sufficiently prevented by resist 8 due to reduction in the film thickness. This results in a problem that buried impurity region 9a joins the surface of substrate 1, as shown in FIG. 17B. FIG. 17A shows the shape of buried impurity layer 9a generated in the case where ions are implanted using an ideal rectangular resist pattern. FIG. 17A is provided for comparison with FIG. 17B.
The aforementioned AZ4620 has a problem set forth in the following.
FIG. 18 is a graph showing the relationship between the time period a semiconductor device was left after the application of a resist solution onto the substrate until the exposure step and the sensitivity. It is appreciated from FIG. 18 that at least 30 minutes is required for the semiconductor device to be left after the application and until the exposure for the purpose of stabilization of the sensitivity. This is because the resist must absorb moisture sufficiently from the atmosphere to achieve thorough light reaction of the photosensitive agent during exposure. (Referring to FIG. 12, H.sub.2 O is indispensable for photodecomposition of the photosensitive agent.)
A resist film of great thickness requires a long time to absorb moisture from the air in comparison with a resist film having the standard film thickness. If the time left until exposure is carried out is short when using a resist film of great film thickness, moisture will not be absorbed sufficiently, leading to a problem that there is deviation in the sensitivity to adversely affect the throughput.
A similar problem is encountered in using a "OFPR550" (a product of Tokyo Ohka Kogyo Co., Ltd), developed as a resist that provides a great film thickness and that allows usage of i-line. A trend is towards using i-line instead of g-line in accordance with miniaturization of LSIs. A resist generally absorbs more g-line than i-line, as shown in FIG. 15. If a g-line resist is exposed by i-line, various problems will be generated such as reduction in sensitivity, degradation of resolution, and degradation of the sectional shape of the resist. OFPR550 was developed to solve these problems. It is a resist designed to allow usage of i-line and that allows great thickness.
A method of forming a resist pattern using OFPR550 will be described hereinafter.
OFPR550 is applied on a silicon substrate to be prebaked on a hot plate at 90.degree. C. for 90 seconds. This results in a resist film of 4.5 .mu.m in thickness on a silicon substrate. Light is selectively directed using an i-line stepper "NSR1755i7A" (a product of Nikon Corporation), followed by a baking process (post exposure baking:PEB) at 110.degree. C. for 90 seconds on a hot plate. Then, developing is carried out with a developer NMD-3 (2.38 wt %) for 65 seconds to obtain a resist pattern. The sensitivity was 1200 msec., and resolution was 2.0 .mu.m line-and-space. Patterns less than 5 .mu.m was peeled off after the developing process. This means that the adherence is poor. In order to enhance the adherence, the silicon substrate was treated with vapor of hexamethyldisilazane (referred to as HMDS hereinafter) prior to application of the resist. This process improves the adherence such that patterns as low as 2 .mu.m line-and-space were not peeled off. However, there was a problem that fine particles of the resist was spattered (referred to as "exposure foaming"). This resist has low heat resistance, and was not satisfactory as a mask for impurity ion implantation, similar to the above described AZ4620.
A conventional technique is described hereinafter for obtaining a resist pattern having a film thickness greater than 3 .mu.m by stacking more than 2 layers of a resist.
Referring to FIG. 19A, the surface of a silicon substrate 1 is treated with vapor of HMDS. This HMDS process is carried out to enhance the adherence between silicon substrate 1 and a resist which will be described afterwards. A g-line resist "MCPR2000H" (a product of Mitsubishi Kasei Corporation) is applied on the HMDS treated silicon substrate 1 to be subjected to a prebaking process on a hot plate at 100.degree. C. for 70 seconds. As a result, a first resist film 9 is formed having a film thickness of 2.0 .mu.m.
Referring to FIG. 19B, g-line light 10 is selectively directed to first resist film 9 with a g-line stepper "NSR1505G6E" (a product of Nikon Corporation) using a desired reticle 3. As a result, an exposed portion 5a and a non-exposed portion 5b are generated in first resist film 9. Then, PEB is carried at 120.degree. C. for 90 seconds.
Referring to FIG. 19C, paddle developing is carried out for 60 seconds using a developer NMD-3 (2.38 wt %), resulting in a first resist pattern 11 of a desired configuration. Next, a deep UV cure process of first resist pattern 11 is carried out. A deep UV cure process is carried out to improve the heat resistance of first resist pattern 11, whereby heat sagging of the resist pattern is prevented during a subsequent process of post baking. Furthermore, it prevents mixing of a subsequent formed second resist film 12 and first resist pattern 11. Following the deep UV cure process, a post baking process of first resist pattern 11 is carried out in an oven at 150.degree. C. for 60 minutes to prevent gas generation during a subsequent ion implantation process.
Referring to FIG. 19D, a second resist film 12 is formed on silicon substrate 1 so as to cover first resist pattern 11 under conditions identical to those for forming the first resist film (same resist, same prebaking condition).
Referring to FIG. 19E, g-line-light 10 is selectively directed to second resist film 12 using reticle 3 identical to that used for formation of first resist film 11. Then, PEB is carried out for second resist film 12 on a hot plate at 120.degree. C. for 90 seconds. Then, paddle developing is carried out for 70 seconds, resulting in a second resist pattern 13 left on first resist pattern 11. Then, a deep UV cure process is carried out for second resist pattern 13 to improve the heat resistance of second resist pattern 13. Also, a post baking process for second resist pattern 13 was carried out at 150.degree. C. for 60 minutes in order to prevent gas generation during a subsequent ion implantation step. Thus, a two layered resist pattern 14 of a first resist pattern 11 and a second resist pattern 13 is obtained.
Referring to FIG. 19G, phosphorus ions 9 are implanted at high energy using the 2-layered resist pattern 14 as a mask. As a result, a buried impurity layer 9a is formed at a deep position in silicon substrate 1.
Referring to FIGS. 19H and 19I, 2-layered resist pattern 14 is removed by ashing by O.sub.2 plasma. This method allows the usage of both the g-line and the i-line. Also, there is no limitation of the type of resist. The problem concerning the adherence between the substrate and the resist, and the problem of gas generation are also solved. Sagging of the resist shape does not occur. Therefore, a resist pattern having a film thickness of greater than 3 .mu.m can be formed without inducing reduction of the resolution. However, this method had a problem that the process is complicated with many processing steps.